In recent years, the circuit scale of a semiconductor integrated circuit apparatus has increased along with function expansion and improvement in performance, and a large number of peripheral circuits are used. On the other hand, to give consideration to the environment and satisfy various power saving regulations, an effective power consumption reduction method is increasingly attracting attention. For example, a method (clock gate) of reducing the total power consumption by stopping supply of clock signals to unnecessary peripheral circuits at the time of operation is used.
Japanese Patent Laid-Open No. 9-237131 describes an arrangement in which when one master device and a plurality of slave devices are connected, a clock signal is supplied to only a slave device that is an access target of the master device. An arrangement in which no clock signal is supplied the slave devices other than the access target is also described. Description is given of an arrangement in which, when a response signal issued by the slave device in response to one access demand (request) is detected, it is determined that access has ended, and supply of clock signals to all devices is stopped.
If, however, the clock gate method described in Japanese Patent Laid-Open No. 9-237131 is used for a system using a ring bus, a clock signal is supplied to only a slave device as an access destination, and slave devices other than the access target cannot operate. As a result, request data and response data cannot be circulated on the ring bus via the slave devices other than the access target on the ring bus. Thus, the arrangements described in Japanese Patent Laid-Open No. 9-237131 cannot be applied to a system that uses a ring bus.